The present invention relates generally to high-speed data interfaces and more particularly to circuitry for ordering clock edges at high-speed data interfaces.
Due to rapid progress in design techniques and process technology, the speed of integrated circuit (IC) devices has increased considerably. Such a rapid change in the speed of IC devices has also led to increasingly demanding requirements on the memory devices that interface with these IC's. Besides having a high storage capacity, modern memory chips must be able to interface with other chips at increasingly faster speeds. Consequently, the use of Double Data Rate (DDR) and Quadruple Data Rate (QDR) memory devices, or more generally a multiple data-rate interface, for faster speed has become increasingly common. A DDR interface is a synchronous (that is, clocked) interface where data is transferred on each edge of a clock signal. Specifically, alternating data bits in a DDR signal are transferred on the rising and falling edges of a clock signal, thereby doubling the peak throughput of the memory device without increasing the system clock frequency. Similar steps and results exist for Low Voltage Differential Signaling (LVDS).
During a DDR transfer from an IC (e.g. an FPGA or PLD) to a memory device for performing a write operation, different data signals are transmitted when the clock signal (CLK) value is 0, a data low (DL), and when it is 1, a data high (DH). The timing of these data signals must be correlated to the timing signal of the clock, which is used to select which data signal to send. The DL signal is transferred for the entire time that the clock signal is zero. The DH signal is transferred for the entire time that the clock signal is one.
The timings of the DL, DH, and CLK signals depend on each one's different routing path within the circuit. The different routing paths create differing delays in the signals. The different delays may cause a failure to satisfy the critical timing criteria, which ensure the proper data signal is selected for transfer to the memory device. This is particularly true when the circuit must be able to operate at varying external conditions (such as temperature) that can affect the delays associated with the different routing paths.
Thus, what are needed are circuits, methods, and apparatus for satisfying the critical timing restraints in an efficient and easily implemented method.